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Pleite Moreno, C. (2011). Speed optimization of a multilayer-board for multi-gigabit/s chip-to-chip interconnects. Universitat Politècnica de València. http://hdl.handle.net/10251/11506
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/11506
Título: | Speed optimization of a multilayer-board for multi-gigabit/s chip-to-chip interconnects | |||
Autor: | Pleite Moreno, Cristina | |||
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The main aim of this project is to increase the data rate communication between a CPU and a DRAM to above 6.5 GHz by optimization of the Printed Circuit Board (PCB) interconnections (these interconnections include vias, ...[+]
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Derechos de uso: | Reserva de todos los derechos | |||
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