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dc.contributor.author | Barreiro, Antonio | es_ES |
dc.contributor.author | Baños, Alfonso | es_ES |
dc.date.accessioned | 2020-05-27T08:40:43Z | |
dc.date.available | 2020-05-27T08:40:43Z | |
dc.date.issued | 2012-10-14 | |
dc.identifier.issn | 1697-7912 | |
dc.identifier.uri | http://hdl.handle.net/10251/144408 | |
dc.description.abstract | [ES] Un sistema de control basado en reset consta de un controlador lineal al que se ha incorporado un mecanismo de reseteo o reinicio a cero del estado. La puesta a cero del estado del controlador (o de alguna de sus coordenadas) se aplica sólo cuando se cumple cierta condición. La condición que activa o dispara el reseteo es normalmente el cruce por cero del error de seguimiento. La idea de control reseteado es antigua, se remonta al controlador de J.C. Clegg de 1958 y fue refundada en la década de los 70 por I. Horowitz, quien hizo hincapié en la capacidad de los sistemas reseteados para superar las limitaciones fundamentales que afectan a sistemas lineales con retardos o con polos o ceros en el semiplano derecho. Abandonada temporalmente, la idea fue retomada en la última década, recibiendo un nuevo impulso por parte de diferentes grupos de investigación que aportan avances en el análisis, diseño y aplicación experimental de sistemas reseteados. Este interés se enmarca en el resurgimiento actual de los sistemas híbridos: un sistema reseteado puede interpretarse como un caso particular de sistema híbrido que, a pesar de su simplicidad, permite aliviar las limitaciones fundamentales lineales. El objetivo de este trabajo es exponer, en forma de tutorial, el panorama actual en este campo. Primero se presenta una reseña histórica sobre las tres principales escuelas: la clásica, que condiciona el reseteo al cruce por cero del error; la ligada a sistemas impulsivos, donde el reseteo es de base temporal; y la enmarcada en sistemas híbridos, que usa una condición sectorial. A continuación se presenta un resumen de resultados sobre análisis (relación con limitaciones fundamentales, estabilidad) para concluir con una serie de propuestas de diseño orientadas al compensador reseteado PI+CI. | es_ES |
dc.description.abstract | [EN] A reset control system is formed by a linear controller endowed with certain resetting mechanism, that sets to zero the state. This zeroing of some of the state coordinates is applied when certain condition holds. The condition that triggers resetting is usually the zero crossing of the tracking error. The idea of re-set control dates back to Clegg Integrator (CI) in 1958, and was adopted in the 70's by I. Horowitz, who emphasized the ability of reset systems to overcome fundamental limitations of linear systems with delays or with poles or zeros in the right half-plane. Left aside for some time, the idea was recovered in the last decade and was given a new impulse by several research teams that contribute with advances in analysis, design and application of reset control systems. This interest appears in the context of the present boom of hybrid systems: a reset system is a particular case of hybrid system that, in spite of its simplicity, enables the possibility of overcoming linear limitations. The objetive of this work is to present, in the form of a tutorial, the current panorama in the field. First, a historical review is introduced, on the three main approaches to reset control: the classical approach (based on zero-crossing of the tracking error), the impulsive approach (where reset is applied on a temporal basis) and the hybrid approach (where some sector reset condition is defined). Next, a summary of results is presented on analysis topics (relation to fundamental limitations, stability) and finally several design proposals are discussed, focused to the tuning of PI+CI compensators. | es_ES |
dc.description.sponsorship | Este trabajo ha sido realizado gracias al apoyo de la Secretaría de Estado de Investigación, Desarrollo e Innovación, bajo los proyectos coordinados DPI-2010-20466-C02-01 y DPI2010-20466-C02-02. | es_ES |
dc.language | Español | es_ES |
dc.publisher | Universitat Politècnica de València | es_ES |
dc.relation.ispartof | Revista Iberoamericana de Automática e Informática industrial | es_ES |
dc.rights | Reconocimiento - No comercial - Sin obra derivada (by-nc-nd) | es_ES |
dc.subject | Hybrid systems | es_ES |
dc.subject | Reset control systems | es_ES |
dc.subject | Fundamental limitations | es_ES |
dc.subject | Clegg Integrator | es_ES |
dc.subject | PI+CI compensator | es_ES |
dc.subject | Control basado en reset | es_ES |
dc.subject | Sistemas impulsivos | es_ES |
dc.subject | Sistemas híbridos | es_ES |
dc.subject | Limitaciones fundamentales | es_ES |
dc.subject | Integrador reseteado o integrador de Clegg (CI) | es_ES |
dc.subject | Controlador PI+CI | es_ES |
dc.subject | Sistema reseteado de primer orden (FORE) | es_ES |
dc.title | Sistemas de Control basados en Reset | es_ES |
dc.title.alternative | Reset Control Systems | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1016/j.riai.2012.09.007 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//DPI2010-20466-C02-02/ES/NUEVAS ESTRATEGIAS EN CONTROL RESETEADO: HERRAMIENTAS DE ANALISIS Y DISEÑO Y APLICACIONES/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.description.bibliographicCitation | Barreiro, A.; Baños, A. (2012). Sistemas de Control basados en Reset. Revista Iberoamericana de Automática e Informática industrial. 9(4):329-346. https://doi.org/10.1016/j.riai.2012.09.007 | es_ES |
dc.description.accrualMethod | OJS | es_ES |
dc.relation.publisherversion | https://doi.org/10.1016/j.riai.2012.09.007 | es_ES |
dc.description.upvformatpinicio | 329 | es_ES |
dc.description.upvformatpfin | 346 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 9 | es_ES |
dc.description.issue | 4 | es_ES |
dc.identifier.eissn | 1697-7920 | |
dc.relation.pasarela | OJS\9572 | es_ES |
dc.contributor.funder | Ministerio de Ciencia e Innovación | es_ES |
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