Gutiérrez, RG.; Torres Carot, V.; Valls Coquillat, J. (2012). Hardware architecture of a gaussian noise generator based on inversion method. IEEE Transactions on Circuits and Systems II: Express Briefs. 59(8):501-505. doi:10.1109/TCSII.2012.2204119
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/35284
Título:
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Hardware architecture of a gaussian noise generator based on inversion method
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Autor:
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Gutiérrez, Roberto G.
Torres Carot, Vicente
Valls Coquillat, Javier
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Entidad UPV:
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Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia
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Fecha difusión:
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Resumen:
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In this brief, we present a hardware-based Gaussian noise generator (GNG) with low hardware cost, high generation rate, and high Gaussian tail accuracy. The proposed generator is based on a piecewise polynomial approximation ...[+]
In this brief, we present a hardware-based Gaussian noise generator (GNG) with low hardware cost, high generation rate, and high Gaussian tail accuracy. The proposed generator is based on a piecewise polynomial approximation of the inverse cumulative distribution function (ICDF). We propose to avoid the area-demanding barrel-shifter of the ICDF approximation by means of creating a new uniform random sequence from the uniform random number generator output. The GNG architecture has been implemented in field-programmable gate array devices, and the implementation results are compared with other published designs, achieving a higher deviation with fewer hardware resources. Our GNG generates 242 Msps of random noise and achieves a tail of 13.1 sigma with 442 slices, two multipliers, and two Block-RAM of a Virtex-II device. The generator output successfully passed commonly used statistical tests. © 2012 IEEE.
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Palabras clave:
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Additive white Gaussian noise (AWGN)
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Inversion method
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Piecewise polynomial approximation
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Additive White Gaussian noise
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Gaussian tails
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Generation rate
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Hardware architecture
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Hardware resources
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Inverse cumulative distribution functions
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Inversion methods
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Low hardware costs
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Random noise
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Random number generators
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Random sequence
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Virtex-II device
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Hardware
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Polynomial approximation
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Random number generation
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Statistical tests
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White noise
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Gaussian noise (electronic)
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Derechos de uso:
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Cerrado |
Fuente:
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IEEE Transactions on Circuits and Systems II: Express Briefs. (issn:
1549-7747
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DOI:
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10.1109/TCSII.2012.2204119
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Editorial:
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Institute of Electrical and Electronics Engineers (IEEE)
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Versión del editor:
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http://dx.doi.org/10.1109/TCSII.2012.2204119
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Código del Proyecto:
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info:eu-repo/grantAgreement/MICINN//TEC2008-06787/ES/ARQUITECTURAS DE FEC PARA SISTEMAS DE COMUNICACIONES DE MUY ALTA VELOCIDAD/
info:eu-repo/grantAgreement/MINECO//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/
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Agradecimientos:
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This work was supported by Fondo Europeo de Desarrollo Regional and the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2008-06787 and Grant TEC2011-27916. This brief was recommended by Associate Editor Y. Ha.
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Tipo:
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Artículo
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