Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers, 2017)
[EN] Nowadays, high performance multicore processors implement
multithreading capabilities. The processes running concurrently on these
processors are continuously competing for the shared resources, not only among
cores, ...
Pons-Escat, Lucía; Sahuquillo Borrás, Julio; Selfa, Vicent; Petit Martí, Salvador Vicente; Pons Terol, Julio(Institute of Electrical and Electronics Engineers, 2020-11-01)
[EN] The Last Level Cache (LLC) plays a key role in the system performance of current multi-cores by reducing the number of long latency main memory accesses. The inter-application interference at this shared resource, ...
Feliu Pérez, Josué(Universitat Politècnica de València, 2013-02-25)
[ES] Con el objetivo de mejorar el rendimiento de los CMPs, parte de la investigación reciente se ha centrado en la planificación de procesos para limitar la contención provocada por el limitado ancho de banda. Hoy en dia, ...
March Cabrelles, José Luis; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Hassan Mohamed, Houcine; Duato Marín, José Francisco(Wiley, 2013-09)
A major design issue in embedded systems is reducing the power consumption because batteries have a limited energy budget. For this purpose, several techniques such as dynamic voltage and frequency scaling (DVFS) or task ...
Castelló i Ferrer, Pau(Universitat Politècnica de València, 2019-10-15)
[ES] En este trabajo nos centramos en la Redes Neuronales Convolucionales (en inglés,
Convolutional Neural Networks o CNN). El auge de este tipo de redes neuronales se debe a su
uso potencial tanto para el reconocimiento ...
Navarro Serra, Carlos(Universitat Politècnica de València, 2018-09-10)
[ES] Hoy en día, los procesadores implementan una serie de prefetchers a lo largo de la
jerarquía de caché del procesador con el objetivo de reducir u ocultar la latencia de los
accesos a memoria y, con ello, mejorar las ...
Duro, José; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio(Institute of Electrical and Electronics Engineers, 2021)
[EN] Photonics are becoming realistic technologies for implementing interconnection networks in near future Exascale supercomputer systems. Photonics present key features to design high-performance and scalable supercomputer ...
Pons-Escat, Lucía; Petit Martí, Salvador Vicente; Pons Terol, Julio; Gómez Requena, María Engracia; Huang, Chaoyi; Sahuquillo Borrás, Julio(IEEE Computer Society, 2023-03-03)
[EN] Cloud systems deploy a wide variety of shared resources and host a large number of tenant applications. To
perform cloud research, a small experimental platform is commonly used, which hides the huge system complexity ...
Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Eeckhout, Lieven(Institute of Electrical and Electronics Engineers, 2020-02-01)
[EN] Resource sharing is a critical issue in simultaneous multithreading (SMT) processors as threads running simultaneously on an SMT core compete for shared resources. Symbiotic job scheduling, which co-schedules applications ...
Feliu Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco(IEEE, 2012-05-21)
In order to improve CMP performance, recent research has focused on scheduling to mitigate contention produced by the limited memory bandwidth. Nowadays, commercial CMPs implement multi-level cache hierarchies where last ...
Pons-Escat, Lucía; Feliu-Pérez, Josué; Puche, José; Huang, Chaoyi; Petit Martí, Salvador Vicente; Pons Terol, Julio; Gómez Requena, María Engracia; Sahuquillo, Julio(Cornell University, 2020-10)
[EN] Understanding inter-VM interference is of paramount importance to provide a sound knowledge and understand where performance
degradation comes from in the current public cloud. With this aim, this paper devises a ...
Petit Martí, Salvador Vicente; Sáez Barona, Sergio; López Rodríguez, Pedro Juan(Universitat Politècnica de València, 2019-07-09)
En el diseño de procesadores segmentados, existen diversas opciones de implementación que permiten resolver los riesgos o conflictos derivados de la ejecución de varias instrucciones en el mismo ciclo del procesador. Estas ...
Feliu Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco(Elsevier, 2013-06)
Performance of current chip multiprocessors (CMPs) is strongly connected with the performance of their last level caches (LLCs), which mainly depends on the cache requirements of the processes as well as their interference. ...
Feliu-Pérez, Josué; Naithani, Ajeya; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Qureshi, Moinuddin; Eeckhout, Lieven(Institute of Electrical and Electronics Engineers, 2022-06-01)
[EN] Modern-day graph workloads operate on huge graphs through pointer chasing which leads to high last-level cache (LLC) miss rates and limited memory-level parallelism (MLP). Simultaneous Multi-Threading (SMT) effectively ...
Titos-Gil, Rubén; Flores, Antonio; Fernández-Pascual, Ricardo; Ros, Alberto; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Acacio, Manuel E.(Institute of Electrical and Electronics Engineers, 2019-11)
[EN] This manuscript opens the way to a new class of coherence directory structures that are based on the brand-new concept of way combining. A Way-Combining Directory (WC-dir) builds on a typical sparse directory but ...
Duro-Gómez, José; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia(IEEE Computer Society, 2018-11-09)
[EN] Exascale computing is the next step in high performance computing provided by systems composed of millions of interconnected processing cores. In order to guide the design and implementation of such systems, multiple ...