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Browsing by Author "Gómez Requena, María Engracia"

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Browsing by Author "Gómez Requena, María Engracia"

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    A Family of Fault-Tolerant Efficient Indirect Topologies 
    Bermúdez Garzón, Diego Fernando; Gómez Requena, Crispín; Gómez Requena, María Engracia; López Rodríguez, Pedro Juan; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2016-04)
    On the one hand, performance and fault-tolerance of interconnection networks are key design issues for high performance computing (HPC) systems. On the other hand, cost should be also considered. Indirect topologies are ...
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    A fault-tolerant routing strategy for k-ary n-direct s-indirect topologies based on intermediate nodes 
    Peñaranda Cebrián, Roberto; Gómez Requena, María Engracia; López Rodríguez, Pedro Juan; Gran, Ernst Gunnar; Skeie, Tor (John Wiley & Sons, 2017)
    [EN] Exascale computing systems are being built with thousands of nodes. The high number of components of these systems significantly increases the probability of failure. A key component for them is the interconnection ...
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    A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches 
    Selfa-Oliver, Vicent; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia (Institute of Electrical and Electronics Engineers, 2017)
    [EN] Shared caches have become the common design choice in the vast majority of modern multi-core and many-core processors, since cache sharing improves throughput for a given silicon area. Sharing the cache, however, has ...
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    A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies 
    Gómez Requena, Crispín; Gilabert Villamón, Francisco; Gómez Requena, María Engracia; López Rodríguez, Pedro Juan; Duato Marín, José Francisco (Springer Verlag (Germany), 2015-07)
    Large cluster-based machines require efficient high-performance interconnection networks. Routing is a key design issue of interconnection networks. Adaptive routing usually outperforms deterministic routing at the expense ...
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    A Research-Oriented Course on Advanced Multicore Architecture 
    Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Selfa Oliver, Vicent; Gómez Requena, María Engracia (IEEE Computer Society, 2015-05)
    Multicore processors have become ubiquitous in our real life in devices like smartphones, tablets, etc. In fact, they are present in almost all segments of the computing market, from supercomputers to embedded devices. The ...
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    A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies 
    Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia; Selfa-Oliver, Vicent (Elsevier, 2017)
    [EN] The fast evolution of multicore processors makes it difficult for professors to offer computer architecture courses with updated contents. To deal with this shortcoming that could discourage students, the most appropriate ...
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    Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework 
    Puche Lara, José; Lechago Buendía, Sergio; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (IEEE, 2016)
    Photonic interconnects are a promising solution for the so-called communication bottleneck in current Chip Multiprocessor (CMPs) architectures. This technology presents an inherent low-latency and power consumption almost ...
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    Adaptive prefetch for multicores 
    Selfa Oliver, Vicent (Universitat Politècnica de València, 2016-01-08)
    [EN] Current multicore systems implement various hardware prefetchers since prefetching can significantly hide the huge main memory latencies. However, memory bandwidth is a scarce resource which becomes critical with ...
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    Adaptive Prefetching and Cache Partitioning for Multicore Processors 
    Selfa Oliver, Vicent (Universitat Politècnica de València, 2018-11-13)
    El acceso a la memoria principal en los procesadores actuales supone un importante cuello de botella para las prestaciones, dado que los diferentes núcleos compiten por el limitado ancho de banda de memoria, agravando la ...
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    An efficient cache flat storage organization for multithreaded workloads for low power processors 
    Puche, José; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Elsevier, 2020-09)
    [EN] The cache hierarchy of current multicores typically consists of three levels, ranging from the faster and smaller L1 level to the slower and larger L3 level. This approach has been demonstrated to be effective in high ...
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    Analysis of opportunities for cache coherence in heterogeneous embedded systems 
    Esteve García, Albert (Universitat Politècnica de València, 2013-06-18)
    [ES] En el contexto de los sistemas empotrados heterogéneos surgen nuevas necesidades y retos. Este trabajo se va a centrar en la coherencia de éstos sistemas para analizar la posibilidad de aplicar técnicas que se ajusten ...
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    Arquitectura de memoria para explotar la localidad y el paralelismo a nivel de banco 
    Duro Gómez, José (Universitat Politècnica de València, 2015-09-29)
    [ES] La memoria principal constituye uno de los principales cuellos de botella de los procesadores manycore. Una de las causas es la arquitectura interna organizada en 8 bancos de las actuales DDR3. Cada banco contiene un ...
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    Bandwidth-Aware Dynamic Prefetch Configuration for IBM POWER8 
    Navarro, Carlos; Feliu-Pérez, Josué; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Institute of Electrical and Electronics Engineers, 2020-08-01)
    [EN] Advanced hardware prefetch engines are being integrated in current high-performance processors. Prefetching can boost the performance of most applications, however, the induced bandwidth consumption can lead the system ...
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    Bringing Real Processorsto Labs 
    Gómez Requena, Crispín; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Wiley, 2015-09)
    The architecture of current processors has experienced great changes in the last years, leading to sophisticated multithreaded multicore processors. The inherent complexity of such processors makes difficult to update ...
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    Caché de directorio multinivel escalable para CMP NUCAs 
    Valls Mompó, Joan Josep (Universitat Politècnica de València, 2012-10-03)
    El propósito de este proyecto es diseñar y evaluar por medio de simulación una nueva estructura de directorio más escalable que los esquemas de caché de directorio tradicionalmente utilizados, así como otros publicados ...
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    Caracterización de Cargas para Redes de Computación Exascale 
    Duro-Gómez, José; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia (Universidad de Zaragoza, 2018-11-09)
    [ES] La computación exascale es el siguiente paso en la computación de alto rendimiento proporcionada por sistemas compuestos por millones de núcleos de procesamiento interconectados. Para guiar el diseño e implementación ...
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    Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors 
    Esteve García, Albert (Universitat Politècnica de València, 2017-09-01)
    Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects ...
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    Design Space Exploration for Networks On-chip 
    Gilabert Villamón, Francisco (Universitat Politècnica de València, 2011-09-12)
    Los diseños multi-núcleo se están convirtiendo en la solución más popular a la mayoría de las limitaciones de los diseños mono-núcleo. Un diseño multi-núcleo sigue el paradigma de diseño conocido como Sistema dentro del ...
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    Efficient Selective Multicore Prefetching under Limited Memory Bandwidth 
    Selfa-Oliver, Vicent; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia; Gómez Requena, Crispín (Elsevier, 2018)
    [EN] Current multicore systems implement multiple hardware prefetchers to tolerate long main memory latencies. However, memory bandwidth is a scarce shared resource which becomes critical with the increasing core count. ...
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    Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors 
    Esteve García, Albert; Ros Bardisa, Alberto; Gómez Requena, María Engracia; Robles Martínez, Antonio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2016-03)
    Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects ...