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Listar por autor "Feliu Pérez, Josué"

Mostrando ítems 1-20 de 30

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A Workload Generator for Evaluating SMT Real-Time Systems

Furió Novejarque, Clara; Feliu-Pérez, Josué; Petit Martí, Salvador Vicente; Duro-Gómez, José; Sahuquillo Borrás, Julio (IEEE Computer Society, 2018-07-16)

[EN] Real-time tasks have experience a significant complexity increase in the last years. We can find examples of real-time tasks in nowadays systems that control self-driving cars or multimedia systems, among others. To ...
Addressing bandwidth contention in SMT multicores through scheduling

Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco (ACM, 2014-06)

To mitigate the impact of bandwidth contention, which in some processes can yield to performance degradations up to 40%, we devise a scheduling algorithm that tackles main memory and L1 bandwidth contention. Experimental ...
Addressing fairness in SMT multicores with a progress-aware scheduler

Feliu Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco (IEEE, 2015-05-25)

Current SMT (simultaneous multithreading) processors co-schedule jobs on the same core, thus sharing core resources like L1 caches. In SMT multicores, threads also compete among themselves for uncore resources like the LLC ...
Bandwidth-Aware Dynamic Prefetch Configuration for IBM POWER8

Navarro, Carlos; Feliu-Pérez, Josué; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Institute of Electrical and Electronics Engineers, 2020-08-01)

[EN] Advanced hardware prefetch engines are being integrated in current high-performance processors. Prefetching can boost the performance of most applications, however, the induced bandwidth consumption can lead the system ...
Bandwidth-Aware On-Line Scheduling in SMT Multicores

Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2016-02)

The memory hierarchy plays a critical role on the performance of current chip multiprocessors. Main memory is shared by all the running processes, which can cause important bandwidth contention. In addition, when the ...
Cache-Hierarchy contention-aware scheduling in CMPs

Feliu Pérez, Josué; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2014-03)

To improve chip multiprocessor (CMP) performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multilevel cache hierarchies that are ...
Cloud White: Detecting and Estimating QoS Degradation of Latency-Critical Workloads in the Public Cloud

Pons-Escat, Lucía; Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia; Petit Martí, Salvador Vicente; Pons Terol, Julio; Huang, Chaoyi (Elsevier, 2023-01)

[EN] The increasing popularity of cloud computing has forced cloud providers to build economies of scale to meet the growing demand. Nowadays, data-centers include thousands of physical machines, each hosting many virtual ...
Contention-Aware Scheduling for SMT Multicore Processors

Feliu Pérez, Josué (Universitat Politècnica de València, 2017-03-27)

The recent multicore era and the incoming manycore/manythread era generate a lot of challenges for computer scientists going from productive parallel programming, over network congestion avoidance and intelligent power ...
DeepP: Deep Learning Multi-Program Prefetch Configuration for the IBM POWER 8

Lurbe Sempere, Manel (Universitat Politècnica de València, 2020-09-28)

[ES] Los procesadores de altas prestaciones más modernos integran prefetchers hardware muy complejos, en los que seleccionar la configuración para que éste obtenga las mejores prestaciones se convierte en una tarea compleja. ...
DeepP: Deep Learning Multi-Program Prefetch Configuration for the IBM POWER 8

Lurbe-Sempere, Manel; Feliu-Pérez, Josué; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Institute of Electrical and Electronics Engineers, 2022-10-01)

[EN] Current multi-core processors implement sophisticated hardware prefetchers, that can be configured by application (PID),to improve the system performance. When running multiple applications, each application can present ...
Designing lab sessions focusing on real processors for computer architecture courses: A practical perspective

Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente (Elsevier, 2018)

[EN] Computer architecture courses typically include lab sessions to reinforce, from a practical perspective, concepts and architectural mechanisms studied in lectures. Lab sessions are mainly based on simulation frameworks ...
Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources

Pons-Escat, Lucía; Feliu-Pérez, Josué; Puche-Lara, José; Huang, Chaoyi; Petit Martí, Salvador Vicente; Pons Terol, Julio; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Elsevier, 2022-06)

[EN] Multithreaded latency-critical applications represent an important subset of workloads running on public cloud systems. Most of these systems deploy powerful computing servers including Intel Hyper-Threading processors. ...
Estudio de prestaciones de cargas de latencia crítica en sistemas SMT

Wu, Dezhen (Universitat Politècnica de València, 2021-03-30)

[ES] La computación en la nube (cloud computing) ofrece servicios de computación bajo demanda a través de una red (habitualmente internet). Es un servicio ampliamente utilizado en la actualidad y, por tanto, existe una ...
Evaluación experimental de los mecanismos de prebúsqueda en el IBM Power8

Carmona Vila, Jahel (Universitat Politècnica de València, 2018-01-03)

[ES] En este proyecto se estudian los mecanismos de prebúsqueda en una máquina con el procesador IBM Power8. Se ejecutan benchmarks SPEC y se estudia el impacto sobre las prestaciones que ejercen los distintos mecanismos ...
Improving IBM POWER8 Performance Through Symbiotic Job Scheduling

Feliu-Pérez, Josué; Eyerman, Stijn; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Eeckhout, Lieven (Institute of Electrical and Electronics Engineers, 2017)

[EN] Symbiotic job scheduling, i.e., scheduling applications that co-run well together on a core, can have a considerable impact on the performance of processors with simultaneous multithreading (SMT) cores. SMT cores share ...
Improving schedulabity on the SMT Multicore Intel Xeon e-5645 under real-time systems

Furió Novejarque, Clara (Universitat Politècnica de València, 2016-10-26)

[EN] Traditionally, the study of real-time systems has mainly focused on hardware systems simple enough that make its study easy; for instance, system modeling and schedulability analysis. This implies that the processors ...
L1-Bandwidth Aware Thread Allocation in Multicore SMT Processors

Feliu Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco (IEEE, 2013)

Improving the utilization of shared resources is a key issue to increase performance in SMT processors. Recent work has focused on resource sharing policies to enhance the processor performance, but their proposals ...
Mejorar las prestaciones del prefetcher utilizando técnicas de deep learning

Lurbe Sempere, Manel (Universitat Politècnica de València, 2019-10-08)

[ES] Recientemente ha habido un gran incremento de aplicaciones de las redes neuronales gracias a nuevas técnicas de aprendizaje profundo (deep learning), un nuevo tipo de aprendizaje automático que ha sido posible gracias ...
Palnificació multinivell per a optimitzar l'ús de l'ample de banda de la jerarquia de memòria en multinuclis

Feliu Pérez, Josué (Universitat Politècnica de València, 2011-07-28)
Perf&Fair: A Progress-Aware Scheduler to Enhance Performance and Fairness in SMT Multicores

Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers, 2017)

[EN] Nowadays, high performance multicore processors implement multithreading capabilities. The processes running concurrently on these processors are continuously competing for the shared resources, not only among cores, ...